Field of the Invention
The invention relates to a manufacturing method of a package structure, and particularly relates to a manufacturing method of a wafer level package structure.
Description of Related Art
In a manufacturing process of a wafer level package (e.g., fan out wafer level package (FO-WLP)), in order to support the wafer after thinning, the wafer is usually placed on a wafer support system (WSS). In this way, the wafer is able to withstand various transport in the manufacturing process and avoid wafer warpage which may cause fragmentation.
FIG. 1A to FIG. 1G are schematic diagrams of a manufacturing process of a conventional wafer level package structure. Referring to FIG. 1A, a conventional wafer support system 11 includes a glass supporting board 12 and a gel layer 13 coated on the glass supporting board 12. Next, as shown in FIG. 1B, a chip 20 having a plurality of conductive pillars 24 is disposed on the wafer support system 11. The chip 20 includes an active surface 21 and a back surface 22 opposite to each other, and a plurality of pads 23 on the active surface 21. The back surface 22 of the chip 20 is fixed to the glass supporting board 12 through the gel layer 13.
Then, as shown in FIG. 1C, a molding 30 is disposed on the wafer support system 11 so as to mold the whole chip 20 and the conductive pillars 24 on the chip 20. After that, as shown in FIG. 1D, the molding 30 is ground to expose the conductive pillars 24.
Then, as shown in FIG. 1E, a redistribution layer (RDL) 40 is manufactured on the chip 20. The RDL 40 is connected to the conductive pillars 24. After that, a dielectric layer 45 having openings 46 is formed on the RDL 40. Furthermore, as shown in FIG. IF, a plurality of solder balls 50 are disposed to the openings 46 so as to be connected to the RDL 40. Lastly, as shown in FIG. 1G, the wafer support system 11 is removed to obtain the conventional wafer level package structure 10.
In the conventional manufacturing process, since a thickness variation of the glass supporting board 12 in different positions of the wafer support system 11 is larger, and the control of flatness and uniformity when coating the gel layer 13 has the manufacturing process limitations, the conductive pillars 24 or the RDL 40 are manufactured on the pads 23 in the conventional manufacturing process to overcome the height difference between different pads 23 after attaching the chip 20 to the wafer support system 11. However, if the flatness of the wafer support system 11 is worse, the required height of the conductive pillars 24 or the RDL 40 is higher, thereby increasing the package cost. Additionally, multiple chemical cleanings are required in the final step of removing the wafer support system 11, and a special test of the cleaning result is also required after chemical cleaning to avoid the gel layer 13 remaining on the glass supporting board 12 or the back surface 22 of the chip 20, so as to affect the subsequent manufacturing process. Thus, the process of removing the wafer support system 11 also requires a certain cost.